The present invention relates generally to semiconductor design technology, and more particularly to a method and apparatus for providing a fast address counter for use with an integrated circuit device.
Speed and timing constraints have always been important considerations in designing electronic systems. Most system designs must match the timing requirements of all the components used, yet still be optimized for high speed. As a result, many integrated circuits, or "chips," utilize a synchronous design. A synchronous chip is one in which components of the chip are connected to a common system clock ("CLK"). Synchronous chips have latches, registers and counters connected to inputs and outputs, all on a single monolithic chip. Furthermore, synchronous chips provide many benefits to system designers, such as fewer external logic chips and higher operation speed.
One example of a synchronous chip is a synchronous dynamic random access memory ("SDRAM") with an on-board address counter. Address counters are commonly used with processors that are capable of burst read or burst write operation. A burst operation is a method of transferring a series of data from one device to another. For example, when a processor initiates a burst read operation to an SDRAM, it provides a base address to denote a memory location in the SDRAM from which a first data is to be read. The processor then expects to read data at one or more memory locations in the SDRAM according to a predetermined burst sequence.
Because the burst sequence has been predetermined, once the first memory location is accessed, counters that are separate from the processor are used to anticipate the next memory locations to be accessed. In so doing, operation of the SDRAM is improved because the counters can quickly generate an address for the next memory location to be accessed, and can initiate the access to that memory location next at an early time.
As processor operation speed, or frequency, has increased, the corresponding speed requirements for the address counters has increased. Therefore, in order to improve operation, address counters have been incorporated onto the SDRAMs themselves, thereby reducing any propagation delays resulting from discrete counters and SDRAMs. However, processor frequency has continued to increase, and simply including a conventional counter inside the SDRAM is not sufficient to meet the strict timing requirements of many modern processors, as described below.
FIG. 1 is a block diagram of a counter, which is designated generally by a reference numeral 10. The counter 10 is incorporated into a SDRAM (not shown). The counter 10 receives an external address from an external address bus XADD. It is understood that supplying an address to a memory device is well known in the art, and will not be further described.
It is a goal of the counter 10 to produce internal addresses on the internal address bus IADD, based upon the external address, in a predetermined burst sequence. Although bursts can be of many different lengths, such as one, two, four, eight or sixteen address locations, an exemplary burst sequence for two addresses A1:A0 of a 32 bit address A31:A0 is:
______________________________________ External Address A31:A2 A1 A0 First Burst Address A31:A2 A1 A0.backslash. Second Burst Address A31:A2 A1.backslash. A0 Third Burst Address A31:A2 A1.backslash. A0.backslash. ______________________________________ (note: the symbol ".backslash." denotes an inverted address)
For the remaining description, the exemplary burst sequence shown above will be used. However, it is understood that other burst sequences and lengths may be used. In addition, it is a goal of the counter 10 to produce an end-of-burst signal WRAPDN, to indicate that the burst sequence is complete. The WRAPDN signal must also meet certain processor-defined set-up and hold times.
The counter 10 includes three address registers 12, 14, 16, an incrementor 20, a subtractor 18, a comparator 22, and a burst sequencer 24. Each of the registers 12, 14, 16 is synchronized by a K signal, which is driven by a clock circuit 26. The K signal is responsive to three control signals: LOAD, CLK and COUNTUP. The LOAD signal indicates when the address bus XADD contains a valid external address. The CLK signal is the system clock, as described above. The COUNTUP signal indicates when, during a burst sequence, the next memory location of the burst sequence may be accessed.
The burst sequencer 24 is programmable for different burst sequences. Using the exemplary burst sequence described above, the burst sequencer 24 simply passes signals straight through without altering them. However, the burst sequencer 24 can be programmed to support different burst sequences.
In operation, the LOAD signal allows the external address on the external address bus XADD to be loaded into the address registers 12, 14, 16. The address register 16 drives the external address on the internal address bus IADD as the first address of the predetermined burst sequence.
The address register 14 drives an intermediate address A1, which is equal to the external address, to the subtractor 18. The subtractor 18 subtracts one from the intermediate address A1 to produce an intermediate address A2, which is equal to the third internal address of the predetermined burst sequence, as shown above.
Meanwhile, the address register 12 drives an intermediate address A3, which is initially equal to the external address, to the incrementor 20. The incrementor 20 adds one to the intermediate address A3 to produce an intermediate address A4, which is equal to the first burst address of the predetermined burst sequence, as shown above. The intermediate address A4 is supplied to the burst sequencer 24, which produces an intermediate address A5 according to the predetermined burst sequence. The intermediate address A5 is then supplied to the address register 16. The address register 16 thereby updates the internal address on the internal address bus IADD to the next address of the predetermined burst sequence.
The intermediate address A4 is also looped back to the address register 12 in order to calculate the next burst address. Furthermore, the intermediate address A4 is supplied to the comparator 22, where it is compared with the intermediate address A2. In this way, once the intermediate address A4 is equal to the third burst address (which is the last address of the predetermined burst sequence), the comparator 22 can assert the WRAPDN signal.
FIG. 2 is a timing diagram for the counter circuit of FIG. 1. The external address, first burst address, second burst address and third burst address are denoted by the reference numerals B0, B1, B2, and B3, respectively.
Of particular importance is the waveform for the WRAPDN signal. The WRAPDN signal is asserted at a time 35, which is determined by a propagation delay 33. The propagation delay 33 is the sum of a first delay 34 and a second delay 36. The first delay 34 is due to the propagation delay of the incrementor 20 when driving the burst address B3. The incrementor 20 drives the burst address B3 on the intermediate address A4 after the intermediate address A3 is equal to the burst address B2. The second delay 36 is a high-going delay caused by propagation through the comparator 22.
Likewise, the WRAPDN signal is de-asserted at a time 38, which is determined by a propagation delay 39. The propagation delay 39 equals a sum of a hold time delay 40 of the incrementor 20 plus a low-going delay 42 caused by propagation through comparator 22.
The delays 33 and 39 create timing problems for the counter 10. For the sake of example, the frequency of the clock signal CLK will be 100 mega-hertz ("MHz"), which provides a period T of 10 nano-seconds ("ns"). A typical time for the delay 34 is 8 ns and for the delay 36 is 2 ns. As a result, the cumulative delay 33 for the assertion of the WRAPDN signal is 10 ns (8 ns+2 ns), or one clock period. Such a delay is too long to meet the set-up time requirements of many conventional processors. As a result, a clock period is wasted while waiting for the assertion of the WRAPDN signal. It would be advantageous if the WRAPDN signal was asserted early enough to save the wasted clock period.